Project Goals

The presence of millions of transistors on the surface in the order of 1mm² results in very localized heating in  these electronic components. These ‘hot spots’, which can go up to several tens of degrees Celsius above the average temperature of the device, can be a source of tampering  of the features of the component. The increasing complexity of electronic systems, whose integration is now three-dimensional, makes it even more difficult to evacuate the heat. The project, COFISIS’ goal  is using nanotechnology to, 1) Reduce the temperature of the localized hot spots in the electronic systems and integrated circuits, with acceptable manufacturing costs, 2) Recover the thermal energy "wasted" by the components to reduce the consumption of energy by the electronic systems.

Principle

• Using high power thermoelectric superlattices.
  A superlattice = multilayer structure consisting of  two materials with a succession of potential barriers. 

• When the barriers are sufficiently small, the emergence of a ballistic thermionic transport can dramatically increase the thermoelectric power of the  superlattices  when  compared  to  the  bulk material, even including  the filtering of the most energetic electrons.

• The proliferation of interfaces reduces the conduction of phonons, which are the main drivers of heat.

The project COFISIS proposes to make super-vertical lattices directly into the silicon, and not by successive deposits of planar layers to provide a technology compatible with industrial manufacturing processes and significantly reduce manufacturing costs.

Challenges

• Fabrication of super-vertical lattices whose width between layers are sufficiently low for even partially optimized ballistic thermionic transport.

• Development of mathematical models for the heat conduction in heterogeneous nanostructures to help the optimization of superlattices.

• Developing tools for measurement of the heat conduction and thermoelectric power, correct to the nanometric scale.

Organisation 

Main actors in the project:

@ ESIEE Paris: Jaya Parasuraman (PhD student), Philippe Basset, Frédéric Marty, Tarik Bourouina
@ CETHIL: Carolina Abs da Cruz (PhD student), Patrice Chantrenne, Séverenne Gomez, Stephane Lefevre, Konstantinos Termentzidis
@ MATEIS: Mathieu Bardoux (post-doc), Xavier Kleber
@ MBDA France: Francois Conseil
@ LPMDI: Yamin Leprince

Related publications

Journals

• "Thermal Conductivity and Thermal Boundary Resistance of Nanostructures", K. Termentzidis, J. Parasuraman, C. Abs Da Cruz, S. Merabia, D. Angelescu, F. Marty, T. Bourouina, X. Kleber, P. Chantrenne and Philippe Basset, Nanoscale Research Letters, vol. 6:288, 2011

• "Nonequilibrium molecular dynamics simulation of the in-plane thermal conductivity of superlattices with rough interfaces", K. Termentzidis, P. Chantrenne and P. Keblinski, Physical Review B, vol. 79, pp. 214307 (9 p), 2009

Conferences

• "Development of vertical superlattices in silicon for on-chip thermal management", J. Parasuraman, M. Bardoux, D. Angelescu, P. Basset and T. Bourouina, Proceeding of the 16th International workshop on Thermal investigations of ICs and Systems, Barcelona (THERMINIC'10), Barcelona, Spain, 2010

• "Development of vertical superlattices in silicon for on-chip thermal management”, J. Parasuraman, P. Basset and M. Bardoux, Proceeding of the 6th Conference on Ph.D. Research in Microelectronics & Electronics (PRIME’10), Berlin, Germany, 2010

• "Collective Fabrication of Inexpensive Superlatices in Silicon for the thermal management of electronic systems", P. Basset, P. Chantrenne and X. Kleber, 4th European Advanced Technology Workshop On Micropackaging and Thermal Management, La Rochelle, France, 2009