-------------------------------------------------------------------------------
-- Title       : AUTOMATIC GENERATION OF VHDL CODE FOR TOP ALGO ega
-- Project     : Automated generation of VHDL with module Gen_vhdl
-------------------------------------------------------------------------------
-- File        : ega_toplevel.vhdl
-- Author      : Pierre NIANG
-- Company     : ESIEE					
-- Department  : A2SI

--file created:lun oct  6 15:01:41 CEST 2003

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--************************ DEFINITION DE UC INFINI (entity et architecture)  ******************************
entity uc_infini is
  port (        rst  : in std_logic;
                en   : out std_logic;
		rfd  : out std_logic;
		afu  : out std_logic;
		rsu  : in std_logic;
		asd  : in std_logic;
		rfu  : in std_logic;
		afd  : in std_logic);
end uc_infini;

architecture OPERATEUR of uc_infini is

Begin
      
      rfd <= rsu;
      afu <= asd;
      en  <= afd OR rst;
      
end OPERATEUR;

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--***************************** DEFINITION DE UC (entity et architecture)  ****************************
entity uc is
generic (nb_bit_compteur :integer:=6 );
port (rsu,afd,rfu,asd, clk,reset    :in std_logic;
      asu,rfd,afu,rsd,en            :out std_logic;
      cpt                           :out std_logic_vector (nb_bit_compteur-1 downto 0));

end uc;
architecture ucff of uc is
signal compteur: std_logic_vector (nb_bit_compteur-1 downto 0):= (others => '0'); --:="000001";
signal tran    : std_logic:='0';
signal fin     : std_logic;
signal init    : std_logic;
signal enable  : std_logic;
begin

--description de unite de controle
en  <= enable;
fin <= compteur(nb_bit_compteur-1);
rfd <= rsu;
asu <= afd and fin;
cpt <=compteur;
enable  <= (rsu and afd) and ((not fin) or asd);
rsd <= rfu and fin;
afu <= reset or (rsu and (not fin)) or (asd or ((not fin) and (rsu and afd)));
init <= reset or ((afd and fin) and asd);

--description du compteur one hot encoding
process (init, clk, enable)
begin
 if (clk' event and clk = '1') and ( init = '1') then
	       compteur(nb_bit_compteur-1 downto 1) <= (others => '0') ;
	       compteur(0) <= '1';

 else if (clk' event and clk = '1') and (enable = '1') then
		tran <= compteur(nb_bit_compteur-1);
		compteur(nb_bit_compteur-1 downto 1) <= compteur (nb_bit_compteur-2 downto 0);
		compteur(0) <= tran;
	end if;
 end if;
end process;

end ucff;

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--**************************  DEFINITION  Mseq OPERATION   ***** **************************
entity floatMseq is
        generic(        insize:integer :=4;
	                outsize:integer :=12;
			nel:integer :=3;
			tel:integer :=8);

	port (
		rst : std_logic;
		inport : in VECTORfloat (insize-1 downto 0) ;
		outport : out VECTORfloat (outsize-1 downto 0) ;
		cpt : in std_logic_vector(nel-1 downto 0);
		en  : in std_logic;
		clk : in std_logic);
end floatMseq;

architecture OPERATEUR of floatMseq is


signal  sortie_tmp : VECTORfloat (outsize-1 downto 0) ;
signal  sortie_tmp2 : VECTORfloat (insize-1 downto 0) ;

begin

process(sortie_tmp, sortie_tmp2)
	begin
		for i in 0 to outsize - 2 loop
			 outport(i) <= sortie_tmp(i);
		end loop;
		outport(outsize-1 downto (outsize-insize)) <= sortie_tmp2;
	end process;



LAST: process(inport)
	begin
		sortie_tmp2 <= inport;
																						 end process;

IMPLO : process (clk, en)
	begin
          if (clk'event and clk = '1') then

                       if (en = '1') then
		          for i in 0 to nel - 1 loop
				if (cpt(i) = '1') then
					sortie_tmp(((insize*(i+1)) -1) downto (i*insize)) <= inport(insize-1 downto 0);
				else
					 sortie_tmp((insize*(i-1)) downto (i*insize)) <= sortie_tmp((insize*(i-1)) downto (i*insize));
				end if;
			  end loop;

			 end if;

	   end if;
        end process;


end OPERATEUR;


--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--*******************************  DEFINITION MULTIPLICATION OPERATION ******************
entity floatArit_mul is
  	generic (     	size1 : integer := 1;
                	tel1  : integer := 16;
			size2 : integer := 1;
			tel2  : integer := 16;
			size3 : integer := 1;
			tel3  : integer := 16
		);
	port (          rst : in std_logic;
			b : in VECTORfloat(size1-1 downto 0);
			a : in VECTORfloat(size2-1 downto 0);
			o : out VECTORfloat(size3-1 downto 0)
		);
end floatArit_mul;

architecture OPERATEUR of floatArit_mul is
signal sortiemul        : signed(2*tel1-1 downto 0);

begin
  sortiemul <= signed(a(0)) * signed(b(0));
    o(0) <= std_logic_vector(sortiemul(tel1-1 downto 0));

end OPERATEUR;



--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--***************************  DEFINITION CONSTANTE OPERATION  *******************************

entity cst1 is
      	generic(          size1 : integer :=9;
                         tel1 : integer :=16
		);
	port (
		o   : out VECTORfloat (size1-1 downto 0)
		);
	end cst1;

architecture OPERATEUR of cst1 is
begin
	o(0) <= conv_std_logic_vector (1,tel1);
	o(1) <= conv_std_logic_vector (-1,tel1);
	o(2) <= conv_std_logic_vector (2,tel1);
	o(3) <= conv_std_logic_vector (-5,tel1);
	o(4) <= conv_std_logic_vector (5,tel1);
	o(5) <= conv_std_logic_vector (8,tel1);
	o(6) <= conv_std_logic_vector (-4,tel1);
	o(7) <= conv_std_logic_vector (9,tel1);
	o(8) <= conv_std_logic_vector (0,tel1);
	









end OPERATEUR;
	

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--**************************   DEFINITION Xseq OPERATION    ********************************

entity floatoneXseq is

        generic(       insize : integer := 8;
	                tel : integer := 8);
	port (       Entree : in  VECTORfloat (insize-1 downto 0) ;
		     sortie : out std_logic_vector(tel-1 downto 0);
		     Commande : in std_logic_vector(insize-1 downto 0)
		     );
end floatoneXseq;

architecture OPERATEUR of floatoneXseq is


begin



  IMPLO : process (Entree,Commande)
          variable tmp : VECTORfloat ( insize-1 downto 0) ;
	  variable tmp_ou : std_logic_vector(insize-1 downto 0);

  	begin
	for i in 0 to (insize - 1) loop
	                for j in 0 to (tel - 1) loop
			           tmp(i)(j) := Entree(i)(j) AND Commande(i);
			end loop;
	end loop;
	for i in 0 to (tel - 1) loop
	                 tmp_ou(0) := tmp(0)(i);
			 for j in 1 to (insize - 1) loop
				tmp_ou(j) := tmp_ou(j-1) OR tmp(j)(i);
			 end loop;
			 Sortie(i) <= tmp_ou(insize-1);
	end loop;

   end process;

end OPERATEUR;

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

entity floatXseq is


generic(  insize:integer := 12;
          outsize:integer := 4;
	  nel:integer   :=3;
	  tel:integer   :=8);

port (          rst : in std_logic;
		inport: in VECTORfloat (insize -1 downto 0) ;
		outport: out VECTORfloat (outsize -1 downto 0) ;
		cpt : in std_logic_vector(nel-1 downto 0)
	);
end floatXseq ;

architecture Xseq_arch of floatXseq is

type   VECTOR_COM is array (natural RANGE <>) of std_logic_vector(insize-1 downto 0);

signal commtemp : std_logic_vector(insize-1 downto 0);
signal tempcom  : VECTOR_COM(0 to outsize-1);


        Component floatoneXseq
	        generic(    insize : integer := 8;
		                   tel : integer := 8);
		port (
				Entree : in  VECTORfloat (insize-1 downto 0);
				sortie : out std_logic_vector(tel-1 downto 0);
				Commande : in std_logic_vector(insize-1 downto 0)
			);
	End component;

begin
        Xseq1 : for i in 0 to outsize -1 generate
	        realXseq: if (insize-outsize>0) generate
			littleXseq:floatoneXseq
				 generic map(insize,tel)
				 port map (inport, outport(i), tempcom(i));
		end generate realXseq;
		diffuse: if (insize-outsize=0) generate
				outport(i) <= inport(i);
		end generate diffuse;

	end generate Xseq1;
sigcom : process(cpt,tempcom,commtemp)
variable iter : integer :=((insize-outsize)/(nel-1));
begin
        if cpt'event then
	       for i in 0 to nel-1 loop
			if cpt(i)='1' then
				tempcom(0)<=('0',others=>'0');
				tempcom(0)((iter*i))<='1';
			end if;
		end loop;
	end if;
	for i in 1 to outsize-1 loop
			tempcom(i)<=tempcom(i-1)(insize-2 downto 0) & '0';
	end loop;
	end process sigcom;

end Xseq_arch;
		    


--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--******************************   DEFINITION ADDITION OPERATION   *********************
entity floatArit_add is
  	generic(      	size1 : integer := 1;
                  	tel1  : integer := 16;
		        size2 : integer := 1;
			tel2  : integer := 16;
			size3 : integer := 1;
			tel3  : integer := 16
		);
	port (
			rst : in std_logic;
			b : in VECTORfloat (size1 -1 downto 0) ;
			a : in VECTORfloat (size2 -1 downto 0) ;
			o : out VECTORfloat (size3 -1 downto 0)
		);
end floatArit_add;

architecture OPERATEUR of floatArit_add is
signal sortieadd        : signed(tel1-1 downto 0);
begin
        sortieadd <= signed(a(0)) + signed(b(0));
	o(0) <= std_logic_vector(sortieadd);

end OPERATEUR;
		



--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--***************************  DEFINITION CONSTANTE OPERATION  *******************************

entity floatcst is
      	generic(          size1 : integer :=1;
                         tel1 : integer :=16
		);
	port (
		o   : out VECTORfloat (size1-1 downto 0)
		);
	end floatcst;

architecture OPERATEUR of floatcst is
begin
	o(0) <= conv_std_logic_vector (0,tel1);
	

end OPERATEUR;
	

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--***************************  DEFINITION CONSTANTE OPERATION  *******************************

entity cst2 is
      	generic(          size1 : integer :=1;
                         tel1 : integer :=16
		);
	port (
		o   : out VECTORfloat (size1-1 downto 0)
		);
	end cst2;

architecture OPERATEUR of cst2 is
begin
	o(0) <= conv_std_logic_vector (-1,tel1);
	

end OPERATEUR;
	

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--***************************   DEFINITION Iseq OPERATION  *********************************

entity floatIterate is
  generic (     size  : integer :=1;
                nel : integer :=3;
		tel : integer :=8
	);
  port (        rst : in std_logic;
		I_init : in VECTORfloat (size-1 downto 0) ;
		inport  : in VECTORfloat (size-1 downto 0) ;
		O_si  : out VECTORfloat (size-1 downto 0) ;
		outport  : out VECTORfloat (size-1 downto 0) ;
		cpt: in std_logic_vector(nel-1 downto 0);
		en  : in std_logic;
		clk : in std_logic
	);
end floatIterate;

architecture OPERATEUR of floatIterate is

  signal Retard  : VECTORfloat (size -1  downto 0) ;

  begin
      I : process (clk)
          begin
	        if (clk'event and (clk = '1')) then
		        if (en = '1') then
			          Retard <= inport;
			end if;
		end if;
	end process I;
			
    process(cpt)
      begin
              if (cpt(0) = '0') then
	                      O_si <= Retard;
	      else
			      O_si <= I_init;
	      end if;
     end process;

     outport <= inport;
end OPERATEUR;
																			




--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--******************************  DEFINITION SUBSTRACTION OPERATION  *****************

entity floatArit_sub is
  	generic(      	size1 : integer := 1;
                  	tel1  : integer := 16;
		        size2 : integer := 1;
			tel2  : integer := 16;
			size3 : integer := 1;
			tel3  : integer := 16
		);
	port (
			rst : in std_logic;
			b : in VECTORfloat (size1 -1 downto 0) ;
			a : in VECTORfloat (size2 -1 downto 0) ;
			o : out VECTORfloat (size3 -1 downto 0)
		);
end floatArit_sub;

architecture OPERATEUR of floatArit_sub is
signal sortiesub        : signed(tel1-1 downto 0);
begin
        sortiesub <= signed(b(0)) - signed(a(0));
	        o(0) <= std_logic_vector(sortiesub);

end OPERATEUR;
		




--******************************  DEFINITION OF LIBRARYS   ******************
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
--******************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--************************************  DEFINITION WINDOW OPERATION ******************

entity floatwindow is
	generic(	size1 : integer := 1;
	                tel1 : integer := 16;
			size2 : integer := 9;
			tel2 : integer := 16);
			
	port (    	clk : in std_logic;
			en  : in std_logic;
			i   : in VECTORfloat(size1-1 downto 0);
			o   : out VECTORfloat(size2-1 downto 0);
			rst : in std_logic);
	 end floatwindow;

architecture OPERATEUR of floatwindow is
	
signal tabvect : VECTORfloat(size2-1 downto 0) ;
begin
o <= tabvect ;

process(rst,clk,en)
	begin
	 if rst = '1' then
	  for i in 0 to (size2-1) loop
	   tabvect(i) <= (others => '0');
	  end loop;
	 elsif (clk'event) and (clk = '1') then
	 	if en = '1' then
	     	tabvect(size2-2 downto 0) <= tabvect(size2-1 downto 1);
	     	tabvect(size2-1) <= i(0);
	 	end if;
	end if;
end process;


end OPERATEUR;



--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--****************************  DEFINITION DIFFUSE OPERATION  **************************

entity floatDiffuse is
      generic(       size:integer :=4;
                      tel:integer :=8);
      port (
		rst : std_logic;
		inport : in VECTORfloat (size-1 downto 0) ;
		outport : out VECTORfloat (size-1 downto 0)
	);
end floatDiffuse;
	
architecture OPERATEUR of floatDiffuse is
begin
        outport <= inport;

end OPERATEUR;
	

--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;


--****************************  DEFINITION ACTUATOR OPERATION  ****************************

entity floatoutput is
        generic(          size1 : integer :=1;
	                  tel1 : integer :=16
		);
	port (
			i  : in VECTORfloat(size1-1 downto 0);
			en  : in std_logic;
			clk : in std_logic;
			rst : in std_logic
		);
	end floatoutput;
	
architecture OPERATEUR of floatoutput is

type tableau is array (9 downto 0) of VECTORfloat (size1-1 downto 0);
signal tabvect : tableau;
signal number : integer := 0;
begin
	PRO : process (rst, clk, en)

	   begin

	          if rst = '1' then
		              for j in 0 to 9 loop
			      	for i in 0 to (size1-1) loop
			             tabvect(j) (i) <= (others => '0');
				end loop;
			     end loop;
		  elsif (clk'event) and (clk = '1') then
		   if en = '1' then
		       if  number < 10 then
				tabvect(number) <= i;
				number <= number +1;
			else
				number <= 0;
			end if;
		   end if;
		 end if;

end process;

end OPERATEUR;
																  


--********************  DEFINITION OF MEMORY  **********************************
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--**************************  DEFINITION OF MEMORY OPERATION *********************

entity floatdelay is 
	generic(	size1 : integer := 9;
			tel1 : integer := 16;
			size2 : integer := 9;
			tel2 : integer := 16
		);
	port(
			i : in VECTORfloat(size1 -1 downto 0);
			o : out VECTORfloat(size2 -1 downto 0);
			en : in std_logic;
			clk : in std_logic;
			rst : in std_logic
	    );
end floatdelay;

architecture OPERATEUR of floatdelay is
signal tabvect : VECTORfloat(size2-1 downto 0) ;
begin

o <= tabvect ;
process(clk,rst,en)
  begin
    if rst = '1' then
	tabvect(0) <= conv_std_logic_vector (1,tel1);
	tabvect(1) <= conv_std_logic_vector (2,tel1);
	tabvect(2) <= conv_std_logic_vector (3,tel1);
	tabvect(3) <= conv_std_logic_vector (4,tel1);
	tabvect(4) <= conv_std_logic_vector (5,tel1);
	tabvect(5) <= conv_std_logic_vector (6,tel1);
	tabvect(6) <= conv_std_logic_vector (7,tel1);
	tabvect(7) <= conv_std_logic_vector (8,tel1);
	tabvect(8) <= conv_std_logic_vector (9,tel1);
	









    elsif (clk'event and clk = '1') then 
    	if en = '1' then
		tabvect <= i;
	end if;
    end if;
end process;
end OPERATEUR;


--***************   DEFINITION OF LIBRARYS  **********

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
--****************************************************

LIBRARY WORK;
USE WORK.definitions.all;

--***************   DEFINITION OF ENTITY   **********************
ENTITY ega_entity IS
	PORT (
		clk : in std_logic;
		rst : in std_logic
	     );

END ega_entity;

--**************   COMPONENT DEFINITIONS   *********************
--************** COMPONENT uc_infini *********************
ARCHITECTURE ega_archi OF ega_entity is
	COMPONENT uc_infini 
		PORT (
			rst : in std_logic;
			en  : out std_logic;
			rsu : in std_logic;
			asd : in std_logic;
			rfu : in std_logic;
			afu : out std_logic;
			rfd : out std_logic;
			afd : in std_logic
		);
		
	END COMPONENT;


--**************   COMPONENT uc   *********************
	COMPONENT uc 
		GENERIC (	nb_bit_compteur  : integer := 3);

		  PORT (	reset  : in std_logic;
		  	 	en   : out std_logic;
				clk  : in std_logic;
		        	rsu  : in std_logic;
				asu  : out std_logic;
				rsd  : out std_logic;
		        	asd  : in std_logic;
		        	rfu  : in std_logic;
		        	afu  : out std_logic;
				rfd  : out std_logic;
		        	afd  : in std_logic;
				cpt  : out std_logic_vector(nb_bit_compteur-1 downto 0)
				);
	END COMPONENT;

--***************  COMPONENT Mseq   ***********************
	COMPONENT floatMseq 
		GENERIC (	insize  : integer := 1;
		  		outsize : integer := 3;
		  		nel : integer := 1;
	  	  		tel : integer := 8
			);      
	      	PORT (	
		  		rst    : in std_logic;
				inport : in VECTORfloat (insize-1 downto 0) ;
				clk : in std_logic;
				outport : out VECTORfloat (outsize-1 downto 0) ;
	    			cpt : in std_logic_vector(nel-1 downto 0);
				en  : in std_logic
			);
	END COMPONENT;

--************************    COMPONENT OPERATOR   **********************
	COMPONENT floatArit_mul 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16;
				size2 : integer := 1;
			        tel2  : integer := 16;
				size3 : integer := 1;
			        tel3  : integer := 16



			);
		PORT (
				b : in VECTORfloat (size1 -1 downto 0) ;
				a : in VECTORfloat (size2 -1 downto 0) ;
				o : out VECTORfloat (size3 -1 downto 0) ;
				



				rst : in std_logic
		     );
	END COMPONENT;

--************** COMPONENT CONSTANTE  *********************
	COMPONENT cst1 
		GENERIC (
				size1 : integer := 9;
			        tel1  : integer := 16

			);
		PORT (
			o : out VECTORfloat (size1 -1 downto 0) 

		     );
	END COMPONENT;

--***************** COMPONENT Xseq    ********************
	COMPONENT floatXseq 
		GENERIC (	insize  : integer := 3;
		  		outsize : integer := 1;
		  		nel : integer := 1;
	  	  		tel : integer := 8
			);
		PORT ( 		
		  		rst : in std_logic;
				inport  : in VECTORfloat (insize-1 downto 0) ;
				outport : out VECTORfloat (outsize-1 downto 0);
	    			cpt : in std_logic_vector(nel-1 downto 0)
		);
	END COMPONENT;


--************************    COMPONENT OPERATOR   **********************
	COMPONENT floatArit_add 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16;
				size2 : integer := 1;
			        tel2  : integer := 16;
				size3 : integer := 1;
			        tel3  : integer := 16



			);
		PORT (
				b : in VECTORfloat (size1 -1 downto 0) ;
				a : in VECTORfloat (size2 -1 downto 0) ;
				o : out VECTORfloat (size3 -1 downto 0) ;
				



				rst : in std_logic
		     );
	END COMPONENT;

--************** COMPONENT CONSTANTE  *********************
	COMPONENT floatcst 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16

			);
		PORT (
			o : out VECTORfloat (size1 -1 downto 0) 

		     );
	END COMPONENT;

--************** COMPONENT CONSTANTE  *********************
	COMPONENT cst2 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16

			);
		PORT (
			o : out VECTORfloat (size1 -1 downto 0) 

		     );
	END COMPONENT;

--************************  COMPONENT ITERATE ********************
	COMPONENT  floatIterate  
		GENERIC (	size : integer :=1;
  				nel  : integer :=3;
				tel  : integer :=8
				);
		PORT (	
		  		rst    : in std_logic;
				I_init : in VECTORfloat (size-1 downto 0) ;
				inport : in VECTORfloat (size-1 downto 0) ;
				clk    : in std_logic;
				O_si   : out VECTORfloat (size-1 downto 0) ;
				outport : out VECTORfloat (size-1 downto 0) ;
	    			cpt    : in std_logic_vector(nel-1 downto 0);
				en     : in std_logic
		);
	END COMPONENT;

--************** COMPONENT SENSOR  *********************
	COMPONENT floatinput 
		GENERIC (	
				size1 : integer := 1;
			        tel1  : integer := 16

			);
		PORT (
				rst : in std_logic;
				clk    : in std_logic;
				en     : in std_logic;
				o : out VECTORfloat (size1 -1 downto 0) 

		     );
	END COMPONENT;

--************************    COMPONENT OPERATOR   **********************
	COMPONENT floatArit_sub 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16;
				size2 : integer := 1;
			        tel2  : integer := 16;
				size3 : integer := 1;
			        tel3  : integer := 16



			);
		PORT (
				b : in VECTORfloat (size1 -1 downto 0) ;
				a : in VECTORfloat (size2 -1 downto 0) ;
				o : out VECTORfloat (size3 -1 downto 0) ;
				



				rst : in std_logic
		     );
	END COMPONENT;

--**************************  COMPONENT WINDOW ***********************
	COMPONENT floatwindow
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16;
				size2 : integer := 9;
			        tel2  : integer := 16


			);
		PORT (
				i : in VECTORfloat (size1 -1 downto 0) ;
				o : out VECTORfloat (size2 -1 downto 0) ;
				


				rst : in std_logic;
				clk : in std_logic;
				en  : in std_logic
		      );
	END COMPONENT;

--**********************   COMPONENT DIFFUSE ****************
	COMPONENT floatDiffuse 
		GENERIC (	size : integer :=1;
				tel  : integer :=8
			);
		PORT (
				rst : in std_logic;
				inport  : in VECTORfloat (size-1 downto 0) ;
				outport : out VECTORfloat (size-1 downto 0) 
		);
	END COMPONENT;


--*************************   COMPONENT ACTUATOR    *****************
	COMPONENT floatoutput 
		GENERIC (
				size1 : integer := 1;
			        tel1  : integer := 16

			);
		PORT (
				rst : in std_logic;
				clk : in std_logic;
				i : in VECTORfloat (size1 -1 downto 0) ;
				

				en  : in std_logic
		     );
	END COMPONENT;

--******************************* COMPONENT MEMORY  *********************
	COMPONENT floatdelay
		GENERIC (
				size1 : integer := 9;
			        tel1  : integer := 16;
				size2 : integer := 9;
			        tel2  : integer := 16


			);
		PORT (
				i : in VECTORfloat (size1 -1 downto 0) ;
				o : out VECTORfloat (size2 -1 downto 0) ;
				


				rst : in std_logic;
				clk : in std_logic;
				en : in std_logic
			);
		END COMPONENT;

signal enableinf : std_logic;
signal rfdinfini : std_logic;
signal afuinfini : std_logic;
signal enable2 : std_logic;
signal compteur2 : std_logic_vector (9 -1 downto 0);
signal rsd2 : std_logic;
signal rfd2 : std_logic;
signal afu2 : std_logic;
signal asu2 : std_logic;
signal enable3 : std_logic;
signal compteur3 : std_logic_vector (9 -1 downto 0);
signal rsd3 : std_logic;
signal rfd3 : std_logic;
signal afu3 : std_logic;
signal asu3 : std_logic;
signal enable8 : std_logic;
signal compteur8 : std_logic_vector (9 -1 downto 0);
signal rsd8 : std_logic;
signal rfd8 : std_logic;
signal afu8 : std_logic;
signal asu8 : std_logic;
signal rsd2rsd8rsd3 : std_logic;
signal asu8asu2asu3 : std_logic;
signal afuinfiniasu3 : std_logic;
signal rsd2rsd8rfdinfini : std_logic;
signal iJoin_adap_o_coeffs : VECTORfloat ( 9 -1 downto 0); 
signal omul : VECTORfloat ( 1 -1 downto 0); 
signal oCoeff2 : VECTORfloat ( 9 -1 downto 0); 
signal iFork_coeffs_o_adap : VECTORfloat ( 1 -1 downto 0); 
signal oadd : VECTORfloat ( 1 -1 downto 0); 
signal ozero : VECTORfloat ( 1 -1 downto 0); 
signal ogain2 : VECTORfloat ( 1 -1 downto 0); 
signal xIterate_acc_x : VECTORfloat ( 1 -1 downto 0); 
signal endIterate_acc_x : VECTORfloat ( 1 -1 downto 0); 
signal ogensig : VECTORfloat ( 1 -1 downto 0); 
signal aFork_windowa_o_acc : VECTORfloat ( 1 -1 downto 0); 
signal bFork_Coeff2_o_acc : VECTORfloat ( 1 -1 downto 0); 
signal bFork_coeffs_o_acc : VECTORfloat ( 1 -1 downto 0); 
signal osub : VECTORfloat ( 1 -1 downto 0); 
signal xfiltaIterate_acc_x : VECTORfloat ( 1 -1 downto 0); 
signal endfiltaIterate_acc_x : VECTORfloat ( 1 -1 downto 0); 
signal ofiltzero : VECTORfloat ( 1 -1 downto 0); 
signal oegamul : VECTORfloat ( 1 -1 downto 0); 
signal oaccmul : VECTORfloat ( 1 -1 downto 0); 
signal owindowa : VECTORfloat ( 9 -1 downto 0); 
signal gDiffuse_mul_o_adap : VECTORfloat ( 1 -1 downto 0); 
signal wFork_windowa_o_adap : VECTORfloat ( 1 -1 downto 0); 
signal ofiltaccmul : VECTORfloat ( 1 -1 downto 0); 
signal aFork_window_o_acc : VECTORfloat ( 1 -1 downto 0); 
signal owindow : VECTORfloat ( 9 -1 downto 0); 
signal oaccadd : VECTORfloat ( 1 -1 downto 0); 
signal ocoeffs : VECTORfloat ( 9 -1 downto 0); 
signal oadapsub : VECTORfloat ( 1 -1 downto 0); 
signal highstate : std_logic :='1';
--************************  CONNEXION UC INFINITE FOR APPLICATION WITH SEQUENTIEL OPERATORS  ***************
 -- Liste des operations controlees par uc_infini uc  : //ega/visu //ega/gain2 //ega/gensig //ega/windowa //ega/coeffs //ega/sub //ega/mul //ega/Coeff2 //ega/window
 -- Liste des uc situees du cote fast en amont de uc_infini uc : uc_2 uc_8 uc_3
 -- Liste des uc situees du cote fast en aval de uc_infini uc  : uc_8 uc_2 uc_3
 begin 
 	uc_infinite : uc_infini
		PORT MAP (
			rst => rst,
			en  => enableinf,
			rsu => highstate,
			asd => highstate,
			rfu => rsd2rsd8rsd3,
			afu => afuinfini,
			rfd => rfdinfini,
			afd => asu8asu2asu3
			);
	rsd2rsd8rsd3 <= rsd2 and rsd8 and rsd3;
	asu8asu2asu3 <= asu8 and asu2 and asu3;

--************************  CONNEXION UC FINITE FOR APPLICATION WITH SEQUENTIEL OPERATORS  ***************
 -- Liste des operations controlees par uc_2 uc  : //ega/filta/Fork_coeffs_o_acc //ega/filta/Iterate_acc_x //ega/filta/acc/mul //ega/filta/acc/add //ega/filta/zero //ega/filta/Fork_windowa_o_acc
 -- Liste des uc situees du cote fast en amont de uc_2 uc : 
 -- Liste des uc situees du cote fast en aval de uc_2 uc  : 

 	uc_2 : uc
		GENERIC MAP (9)
		PORT MAP (
			reset => rst,
			en  => enable2,
			clk => clk,
			rsu => rfdinfini,
			asu => asu2,
			rsd => rsd2,
			asd => afuinfiniasu3,
			rfu => rfd2,
			afu => afu2,
			rfd => rfd2,
			afd => afu2,
			cpt => compteur2
			);
		
		afuinfiniasu3 <= afuinfini and asu3;
		
		

--************************  CONNEXION UC FINITE FOR APPLICATION WITH SEQUENTIEL OPERATORS  ***************
 -- Liste des operations controlees par uc_3 uc  : //ega/Diffuse_mul_o_adap //ega/Fork_windowa_o_adap //ega/Fork_coeffs_o_adap //ega/Join_adap_o_coeffs //ega/adap/sub //ega/adap/mul
 -- Liste des uc situees du cote fast en amont de uc_3 uc : 
 -- Liste des uc situees du cote fast en aval de uc_3 uc  : 

 	uc_3 : uc
		GENERIC MAP (9)
		PORT MAP (
			reset => rst,
			en  => enable3,
			clk => clk,
			rsu => rsd2rsd8rfdinfini,
			asu => asu3,
			rsd => rsd3,
			asd => afuinfini,
			rfu => rfd3,
			afu => afu3,
			rfd => rfd3,
			afd => afu3,
			cpt => compteur3
			);
		rsd2rsd8rfdinfini <= rsd2 and rsd8 and rfdinfini;
		
		
		

--************************  CONNEXION UC FINITE FOR APPLICATION WITH SEQUENTIEL OPERATORS  ***************
 -- Liste des operations controlees par uc_8 uc  : //ega/filt/Iterate_acc_x //ega/filt/zero //ega/filt/acc/mul //ega/filt/acc/add //ega/filt/Fork_Coeff2_o_acc //ega/filt/Fork_window_o_acc
 -- Liste des uc situees du cote fast en amont de uc_8 uc : 
 -- Liste des uc situees du cote fast en aval de uc_8 uc  : 

 	uc_8 : uc
		GENERIC MAP (9)
		PORT MAP (
			reset => rst,
			en  => enable8,
			clk => clk,
			rsu => rfdinfini,
			asu => asu8,
			rsd => rsd8,
			asd => afuinfiniasu3,
			rfu => rfd8,
			afu => afu8,
			rfd => rfd8,
			afd => afu8,
			cpt => compteur8
			);
		
		afuinfiniasu3 <= afuinfini and asu3;
		
		

--**************************** CONNEXION OF Mseq OPERATOR ********************
 -- La reference de loperation Mseq : Join_adap_o_coeffs
 -- Le chemin de loepation Mseq : //ega/Join_adap_o_coeffs
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3

 	Join_adap_o_coeffs : floatMseq
		GENERIC MAP (1, 9, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => oadapsub,
			outport => iJoin_adap_o_coeffs,
			cpt     => compteur3,
			clk     => clk,
			en      => enable3
			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : mul
 -- Le chemin de loperation : //ega/adap/mul
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3

	mul : floatArit_mul
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		b => gDiffuse_mul_o_adap,
		a => wFork_windowa_o_adap,
		o => omul



		);

--**************************** CONNEXION OF CONSTANTE OPERATOR ********************
 -- La reference de loperation Constante : Coeff2
 -- Le chemin de loperation Constante : //ega/Coeff2
 -- Cette operation appartient a la frontiere numero infini donc de uc infini

 	Coeff2 : cst1
		GENERIC MAP ( 9, 16 )

		PORT MAP (
			o => oCoeff2

			);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_coeffs_o_adap
 -- Le chemin de loepation Xseq : //ega/Fork_coeffs_o_adap
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3
 
 	Fork_coeffs_o_adap : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => ocoeffs,
			outport => iFork_coeffs_o_adap,
			cpt     => compteur3
			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : add
 -- Le chemin de loperation : //ega/filt/acc/add
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8

	add : floatArit_add
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		b => xIterate_acc_x,
		a => ofiltaccmul,
		o => oadd



		);

--**************************** CONNEXION OF CONSTANTE OPERATOR ********************
 -- La reference de loperation Constante : zero
 -- Le chemin de loperation Constante : //ega/filta/zero
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2

 	zero : floatcst
		GENERIC MAP ( 1, 16 )

		PORT MAP (
			o => ozero

			);

--**************************** CONNEXION OF CONSTANTE OPERATOR ********************
 -- La reference de loperation Constante : gain2
 -- Le chemin de loperation Constante : //ega/gain2
 -- Cette operation appartient a la frontiere numero infini donc de uc infini

 	gain2 : cst2
		GENERIC MAP ( 1, 16 )

		PORT MAP (
			o => ogain2

			);

--**************************** CONNEXION OF Iterate OPERATOR ********************
 -- La reference de loperation Iterate : Iterate_acc_x
 -- Le chemin de loepation Iterate : //ega/filt/Iterate_acc_x
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8
 
 	Iterate_acc_x : floatIterate
		GENERIC MAP (1, 9, 16)
		PORT MAP (
			rst     => rst,
			clk     => clk,
			en      => enable8,
			cpt     => compteur8,
			I_init  => ofiltzero,
			inport  => oadd,
			O_si    => xIterate_acc_x,
			outport => endIterate_acc_x
			);

--**************************** CONNEXION OF SENSOR OPERATOR ********************
 -- La reference de loperation Sensor : gensig
 -- Le chemin de loperation Sensor : //ega/gensig
 -- Cette operation appartient a la frontiere numero infini donc de uc infini

 	gensig : floatinput
		GENERIC MAP ( 1, 16 )
 
		PORT MAP (
			rst => rst,
			clk => clk,
			en  => enableinf,
			o => ogensig

			);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_windowa_o_acc
 -- Le chemin de loepation Xseq : //ega/filta/Fork_windowa_o_acc
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2
 
 	Fork_windowa_o_acc : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => owindowa,
			outport => aFork_windowa_o_acc,
			cpt     => compteur2
			);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_Coeff2_o_acc
 -- Le chemin de loepation Xseq : //ega/filt/Fork_Coeff2_o_acc
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8
 
 	Fork_Coeff2_o_acc : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => oCoeff2,
			outport => bFork_Coeff2_o_acc,
			cpt     => compteur8
			);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_coeffs_o_acc
 -- Le chemin de loepation Xseq : //ega/filta/Fork_coeffs_o_acc
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2
 
 	Fork_coeffs_o_acc : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => ocoeffs,
			outport => bFork_coeffs_o_acc,
			cpt     => compteur2
			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : sub
 -- Le chemin de loperation : //ega/sub
 -- Cette operation appartient a la frontiere numero infini donc de uc infini

	sub : floatArit_sub
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		b => endIterate_acc_x,
		a => endfiltaIterate_acc_x,
		o => osub



		);

--**************************** CONNEXION OF Iterate OPERATOR ********************
 -- La reference de loperation Iterate : filtaIterate_acc_x
 -- Le chemin de loepation Iterate : //ega/filta/Iterate_acc_x
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2
 
 	filtaIterate_acc_x : floatIterate
		GENERIC MAP (1, 9, 16)
		PORT MAP (
			rst     => rst,
			clk     => clk,
			en      => enable2,
			cpt     => compteur2,
			I_init  => ozero,
			inport  => oaccadd,
			O_si    => xfiltaIterate_acc_x,
			outport => endfiltaIterate_acc_x
			);

--**************************** CONNEXION OF CONSTANTE OPERATOR ********************
 -- La reference de loperation Constante : filtzero
 -- Le chemin de loperation Constante : //ega/filt/zero
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8

 	filtzero : floatcst
		GENERIC MAP ( 1, 16 )

		PORT MAP (
			o => ofiltzero

			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : egamul
 -- Le chemin de loperation : //ega/mul
 -- Cette operation appartient a la frontiere numero infini donc de uc infini

	egamul : floatArit_mul
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		b => ogain2,
		a => osub,
		o => oegamul



		);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : accmul
 -- Le chemin de loperation : //ega/filta/acc/mul
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2

	accmul : floatArit_mul
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		a => aFork_windowa_o_acc,
		b => bFork_coeffs_o_acc,
		o => oaccmul



		);

--**************************** CONNEXION OF WINDOW   *********************
 -- La reference de loperation : windowa
 -- Le chemin de loperation : //ega/windowa
 -- Cette operation appartient a la frontiere numero infini donc de uc infini
 
 	windowa : floatwindow
	GENERIC MAP ( 1, 16, 9, 16 )


	PORT MAP (
		rst => rst,
		en  => enableinf,
		clk => clk,
		i => ogensig,
		o => owindowa


		);

--**************************** CONNEXION OF Diffuse OPERATOR ********************
 -- La reference de loperation Diffuse : Diffuse_mul_o_adap
 -- Le chemin de loepation Diffuse : //ega/Diffuse_mul_o_adap
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3

 	Diffuse_mul_o_adap : floatDiffuse
		GENERIC MAP (1, 16)
		PORT MAP (
			rst    => rst,
			inport  => oegamul,
			outport => gDiffuse_mul_o_adap
			);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_windowa_o_adap
 -- Le chemin de loepation Xseq : //ega/Fork_windowa_o_adap
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3
 
 	Fork_windowa_o_adap : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => owindowa,
			outport => wFork_windowa_o_adap,
			cpt     => compteur3
			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : filtaccmul
 -- Le chemin de loperation : //ega/filt/acc/mul
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8

	filtaccmul : floatArit_mul
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		a => aFork_window_o_acc,
		b => bFork_Coeff2_o_acc,
		o => ofiltaccmul



		);

--**************************** CONNEXION OF Xseq OPERATOR ********************
 -- La reference de loperation Xseq : Fork_window_o_acc
 -- Le chemin de loepation Xseq : //ega/filt/Fork_window_o_acc
 -- Cette operation appartient a la frontiere numero 8 donc de uc 8
 
 	Fork_window_o_acc : floatXseq
		GENERIC MAP (9, 1, 9, 16)
		PORT MAP (
			rst     => rst,
			inport  => owindow,
			outport => aFork_window_o_acc,
			cpt     => compteur8
			);

--**************************** CONNEXION OF WINDOW   *********************
 -- La reference de loperation : window
 -- Le chemin de loperation : //ega/window
 -- Cette operation appartient a la frontiere numero infini donc de uc infini
 
 	window : floatwindow
	GENERIC MAP ( 1, 16, 9, 16 )


	PORT MAP (
		rst => rst,
		en  => enableinf,
		clk => clk,
		i => ogensig,
		o => owindow


		);

--**************************** CONNEXION OF ACTUATOR OPERATOR ********************
 -- La reference de loperation Actuator : visu
 -- Le chemin de loperation Actuator : //ega/visu
 -- Cette operation appartient a la frontiere numero infini donc de uc infini
 
	visu : floatoutput
		GENERIC MAP ( 1, 16 )

		PORT MAP (
			rst => rst,
			clk => clk,
			en  => enableinf,
			i => osub

			);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : accadd
 -- Le chemin de loperation : //ega/filta/acc/add
 -- Cette operation appartient a la frontiere numero 2 donc de uc 2

	accadd : floatArit_add
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		b => xfiltaIterate_acc_x,
		a => oaccmul,
		o => oaccadd



		);

--**************************  CONNEXION OF MEMORY  ******************************
-- La reference de loperation : coeffs
-- Le chemin de loperation : //ega/coeffs
-- Cette operation appartient a la frontiere numero infini donc de uc infini

	coeffs : floatdelay
	GENERIC MAP ( 9, 16, 9, 16 )


	PORT MAP (
		rst => rst,
		en  => enableinf,
		clk => clk,
		i => iJoin_adap_o_coeffs,
		o => ocoeffs


		);

--**************************** CONNEXION OF OPERATOR ********************
 -- La reference de loperation : adapsub
 -- Le chemin de loperation : //ega/adap/sub
 -- Cette operation appartient a la frontiere numero 3 donc de uc 3

	adapsub : floatArit_sub
	GENERIC MAP ( 1, 16, 1, 16, 1, 16 )



	PORT MAP (
		rst => rst,
		a => iFork_coeffs_o_adap,
		b => omul,
		o => oadapsub



		);

END ega_archi;
-- BEGIN COMPILE SCRIPT
--    vcom definition_ega_archi.vhdl
      
--	vcom inputvectint.vhdl
	
--    vcom ega_archi_toplevel.vhdl